IC Design

Digital system design and system-on-chip integration and verification is one of the core competencies of Integro Silicon. Design of special digital blocks with power, timing, or area constraints could be the target of any product specification. Our team is highly experienced in deployment of industry-standard tools including Synopsys and Cadence. We bring final working products in fast and reliable process with a small number of iterations.

 

    • Turn-key Solution for IC/Module Design
    • Design from Specifications to Chip Layout
    • Chip-level Integration of a system including:
      1. Processors
      2. HW accelerators
      3. Signal processing engines
      4. Encryption engines
      5. Third-party IPs

Competitive Advantages

  • Skillful and agile team
  • Existing silicon-proven IP cores
  • Ready-to-go setup and flow
  • Lower risk of operation
  • Lower OPEX
  • Low engineering cost
  • 15+ years of successful IC design in different process technologies

Assist you to specify the requirements for your systems targeting ASIC flow.

The simulations with specially developed EDA tools give precise predictions about the function and efficiency of final ASICs.

Integro Silicon specialized in IC design brings your idea from concept down to GDS. We can offer the following design services at very low cost:

a. HDL design and verification
b. Frontend synthesis
c. Backend flow (Layout generation, extraction, timing analysis, power estimation,…, final integration)
d. Formal verification

2. Collaboration with analog/RF team on mixed design
3. Embedded software development (Bare-metal/Linux)
4. Hands-on ARM architecture (Processor, AXI/AMBA, slave design, verification)
5. Skillful on FPGA (Zynq, Kintex, Ultrascale)
6. Hardware accelerator

Design Flow

Our design flow comprises all detail and fine-grained processes from concept to RTL and then to GDSII that is delivered to fabrication houses for manufacturing. Hands on industry leader tools from Cadence, Synopsys and Mentor gain a higher level of reliability and helps realization of first-time working silicon for almost all of our products.

Verification is one of the key elements in our flow including exact timing and power analysis as well as handling signal integrity issues that have become serious problems in DSM era. Also, for board-level verifications and prototyping we employ Xilinx FPGAs.

  1. Feasibility study
  2. High-level Block diagram
  3. Cycle-accurate modelling (Matlab flow)
  4. HDL coding
  5. Functional simulation
  6. System integration
  7. FPGA synthesis/P&R/Emulation mainly for digital part
  8. Logic verification using UVM
  9. Extensive testbenches for System-level verification
  10. Constraint Development
  11. ASIC synthesis.
  12. DFT Insertion & ATPG
  13. Static Timing Analysis & Closure
  14. Place and Route
  15. Logic Equivalency Checking
  16. Analog/RF integration
  17. Design rule check
  18. Total LVS (Digital+Analog/RF)
  19. Final GDS & Sign-off

Post-fab activity

  1. Package selection
  2. Test board PCB design
  3. PCB assembly (chip + peripherals)
  4. Load testbenches
  5. Physical/Environment test (power, speed, temperature,…)

Chip Fabrication Model

For manufacturing of the ASIC chips, Integro uses a fabless model which gives access to a different range of chip fabrication technologies. Digital and mixed-signal technologies are used to fabricate the chip products. The chips are manufactured using advanced technology services of reputable foundries.